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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>FMOV (vector, immediate) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">FMOV (vector, immediate)</h2>
      <p class="aml">Floating-point move immediate (vector). This instruction copies an immediate floating-point constant into every element of the SIMD&amp;FP destination register.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_per_half">Half-precision</a>
       and 
      <a href="#iclass_single_and_double">Single-precision and double-precision</a>
    </p>
    <h3 class="classheading"><a id="iclass_per_half"/>Half-precision<span style="font-size:smaller;"><br/>(FEAT_FP16)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">0</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">a</td><td class="lr">b</td><td class="lr">c</td><td class="l">1</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr">1</td><td class="lr">d</td><td class="lr">e</td><td class="lr">f</td><td class="lr">g</td><td class="lr">h</td><td colspan="5" class="lr">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="FMOV_asimdimm_H_h"/><p class="asm-code">FMOV  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t_1" title="Arrangement specifier (field &quot;Q&quot;) [4H,8H]">&lt;T&gt;</a>, #<a href="#sa_imm" title="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;a:b:c:d:e:f:g:h&quot;)">&lt;imm&gt;</a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveFP16Ext.0" title="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;

integer rd = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);

integer datasize = if Q == '1' then 128 else 64;
bits(datasize) imm;

bits(8) imm8 = a:b:c:d:e:f:g:h;
bits(16) imm16 = imm8&lt;7&gt;:NOT(imm8&lt;6&gt;):<a href="shared_pseudocode.html#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;6&gt;, 2):imm8&lt;5:0&gt;:<a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(6);

imm = <a href="shared_pseudocode.html#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm16, datasize DIV 16);</p>
    <h3 class="classheading"><a id="iclass_single_and_double"/>Single-precision and double-precision</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">op</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">a</td><td class="lr">b</td><td class="lr">c</td><td class="l">1</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr">d</td><td class="lr">e</td><td class="lr">f</td><td class="lr">g</td><td class="lr">h</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td/><td/><td colspan="10"/><td/><td/><td/><td colspan="4" class="droppedname">cmode</td><td/><td/><td/><td/><td/><td/><td/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">Single-precision<span class="bitdiff"> (op == 0)</span></h4><a id="FMOV_asimdimm_S_s"/><p class="asm-code">FMOV  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;Q&quot;) [2S,4S]">&lt;T&gt;</a>, #<a href="#sa_imm" title="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;a:b:c:d:e:f:g:h&quot;)">&lt;imm&gt;</a></p></div><div class="encoding"><h4 class="encoding">Double-precision<span class="bitdiff"> (Q == 1 &amp;&amp; op == 1)</span></h4><a id="FMOV_asimdimm_D2_d"/><p class="asm-code">FMOV  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.2D, #<a href="#sa_imm" title="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;a:b:c:d:e:f:g:h&quot;)">&lt;imm&gt;</a></p></div><p class="pseudocode">integer rd = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);

integer datasize = if Q == '1' then 128 else 64;
bits(datasize) imm;
bits(64) imm64;

if cmode:op == '11111' then
    // FMOV Dn,#imm is in main FP instruction set
    if Q == '0' then UNDEFINED;

imm64 = <a href="shared_pseudocode.html#impl-shared.AdvSIMDExpandImm.3" title="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, a:b:c:d:e:f:g:h);
imm = <a href="shared_pseudocode.html#impl-shared.Replicate.2" title="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm64, datasize DIV 64);</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vd&gt;</td><td><a id="sa_vd"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t_1"/>
        <p>For the half-precision variant: is an arrangement specifier, 
      encoded in
      <q>Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">4H</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">8H</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr><tr><td/><td><a id="sa_t"/>
        <p>For the single-precision variant: is an arrangement specifier, 
      encoded in
      <q>Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">2S</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">4S</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;imm&gt;</td><td><a id="sa_imm"/>
        
          <p class="aml">Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h". For details of the range of constants available and the encoding of &lt;imm&gt;, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Modified immediate constants in A64 floating-point instructions</a>.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();

<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[rd, datasize] = imm;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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